Electronic converter, related audio system, integrated circuit and method of operating an electronic converter

ABSTRACT

A converter includes a first switch coupled between a first input terminal and a first terminal of an inductor, and a second switch coupled between a second terminal of the inductor and a second input terminal. A third switch is coupled between the second terminal of the inductor and a first output terminal, and a fourth switch is coupled between the first terminal of the inductor and a second output terminal. A capacitor is coupled between the first and second output terminals. A control circuit monitors a regulated voltage between the first and second output terminals. During a charge phase, the first and second switches are closed to charge the inductor. During a discharge phase, the third and fourth switches are closed to charge the capacitor and increase the regulated voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Italian Patent Application No.102018000002464, filed on Feb. 7, 2018, which application is herebyincorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to an electronic system andmethod, and, in particular embodiments, to an electronic converter,related audio system, integrated circuit and method of operating anelectronic converter.

BACKGROUND

FIG. 1 shows a typical audio system. In the example considered, thesystem comprises an audio signal generator 10, such as a radio, CD 0 MP3player, generating an analog audio signal AS to be sent to at least onespeaker SPK.

In the example considered, an audio amplifier 20 is connected betweenthe audio signal generator 10 and the speaker SPK, which is configuredto generate an amplified audio signal AAS by amplifying the analog audiosignal AS provided by the audio signal generator 10.

For example, FIG. 2 shows a possible implementation of a so-calledclass-D audio amplifier 20. Specifically, in the example considered, theaudio amplifier 20 comprises a waveform generator 202 generating aperiodic triangular waveform signal TS, having typically a frequencybetween 250 kHz and 2.5 MHz. The triangular waveform signal TS is senttogether with the audio signal AS to a comparator 204, which comparesthe audio signal AS with the triangular waveform signal TS therebygenerating a square wave signal DS, whose duty-cycle varies as afunction of the amplitude of the audio signal AS. The square wave signalDS is then amplified by an amplifier stage 206, thereby generating anamplified square wave signal ADS.

For example, FIG. 3 shows an example of the amplifier stage 206, whichcomprises a half-bridge comprising two electronic switches SW1 and SW2,such as (n-channel) Field Effect Transistors (FET), connected in seriesbetween two terminals 210 and 212 adapted to receive a DC supply voltageV_(bat), such as a voltage provided by a battery. Usually, the(negative) terminal 212 represent a ground GND. In the exampleconsidered, the control terminals of the switches SW1 and SW2 (e.g., thegate terminals of respective transistors) are driven as a function ofthe digital signal DS. For example, in the example considered are showntwo driver circuits 2062 and 2064 for the electronic switches SW1 andSW2, and a control circuit 2060 configured to generate the controlsignals for the driver circuits 2062 and 2064 as a function of thedigital signal DS. Substantially, the amplifier 206 is configured toconvert the amplitude of the digital signal DS to the value of thevoltage received at the terminals 210 and 212, which generally isgreater than the voltage of the digital signal DS. For example, thelevel of the signal DS may be 3 VDC and the voltage V_(bat) may be 12VDC. Accordingly, the square wave signal ADS at the intermediate pointbetween the two switches SW1 and SW2 corresponds to an amplified versionof the signal DS.

Finally, the amplified square wave signal ADS is sent to a low-pass orbandpass filter 208, which removes at least the high-frequency spectrumfrom the amplified signal square wave signal ADS, thereby generating anamplified audio signal AAS, which is proportional to the original audiosignal AS.

For example, FIG. 4 shows an example a LC filter 208. Generally, thefilter stage 208 comprises two input terminals for receiving the signalADS provided by the amplifier stage 206, e.g., the input terminals areconnected the intermediate point of the half-bridge and the ground GNDshown in FIG. 3. Moreover, the filter stage 208 comprises two outputterminals for connection to the speaker SPK. Specifically, in theexample considered, the first input terminal is connected to the firstoutput terminal via an inductor L, and the second input terminal and thesecond output terminal are short circuited to ground GND. Finally, acapacitance C is connected in parallel with the output, i.e., betweenthe output terminals. Substantially similar (active or passive) low-passor bandpass filters 208 are provided in most audio amplifier circuitsand/or may be integrated also within the speaker SPK.

Accordingly, a class-D amplifier is based on the fact that the switchingfrequency of the amplifier 20 is significantly higher than the usualaudio band (between 20 Hz and 20 kHz) and accordingly the high switchingfrequency may be filtered with the filter stage 208, therebyreconstructing the profile of the original audio signal AS.

In the context of digital audio data, the signal generator 10 maycomprise an analog-to-digital converter (ADC) for generating the signalAS or the signal generator 10 may provide directly the digital signalDS. Accordingly, the blocks 202 and 204 are purely optional.

Generally, the audio system may also use a plurality of speakers SPK,such as two or four, with respective audio amplifiers 20 using differentsignals AS/DS.

Those of skill in the art will appreciate that the audio system usuallycomprises also one or more electronic converters 30 configured togenerate the regulated supply voltages for the various blocks of theaudio system, such as the supply voltage for the audio signal generator10 and possibly the blocks 202 and 204 in order to generate thedigital/binary signal DS, the supply signals for the control circuit2060 and the driver circuits 2062 and 2064, etc.

For example, usually the converter 30 comprises a DC/DC converter, suchas a converter configured to convert the voltage V_(bat) into a lowersupply voltage, such as a voltage between 1.5 and 3.3 VDC, e.g., 1.8VDC, used by the digital circuits of the audio system and/or the lowpower analog processing circuits. Similarly, additional regulatedvoltages may be generated for the driver circuits 2062 and 2064, such as4.5 VDC for the driver circuit 2064.

In case of a car radio, the design of the various components of theaudio system may be challenging, because of the large variations ofvoltage V_(bat) of the automotive battery. For example, during crank anddump, a typical battery voltage of 14.4V may sharply (in less than 2 ms)drop down to 4-5V or rise up to 40V. For a proper operation, theelectronic converter 30 should thus be able to control the supplyvoltages of the audio system for all battery conditions.

SUMMARY

Various embodiments relate to electronic converters for audio systems,such as class-D audio amplifiers.

Various embodiments relate to generating a regulated voltage.

In various embodiments, the electronic converter comprises two inputterminals configured to receive a supply voltage and two outputterminals configured to provide a regulated voltage.

In various embodiments, the electronic converter comprises an inductorcomprising a first and a second terminal. A first electronic switch isconnected between the first input terminal and the first terminal of theinductor. A second electronic switch is connected between the secondterminal of the inductor and the second input terminal.

In various embodiments, the electronic converter further comprises athird electronic switch connected between the second terminal of theinductor and the first output terminal and a fourth electronic switch isconnected between the first terminal of the inductor and the secondoutput terminal. A capacitor is connected between the first outputterminal and the second output terminal.

In various embodiments, a control circuit monitors the voltage betweenthe two output terminals. During a charge phase, the control circuitcloses the first and the second electronic switch, thereby increasingthe current flowing through the inductor. During a discharge phase, thecontrol circuit closes the third and the fourth electronic switch,whereby the current flowing through the inductor charges the capacitor,thereby increasing the voltage between the two output terminals.

In various embodiments, the control circuit regulates the duration ofthe charge phase and/or the discharge phase, such that the voltagebetween the two output terminals corresponds to a requested value. Forexample, the control circuit may determine whether, at the end of thedischarge phase, the voltage between the two output terminals is greaterthan the requested value. When, at the end of the discharge phase, thevoltage between the two output terminals is smaller than the requestedvalue, the control circuit may increase the duration of the chargephase. Conversely, when, at the end of the discharge phase, the voltagebetween the two output terminals is greater than the requested value,the control circuit may decrease the duration of the charge phase.

Generally, the electronic converter may also comprise one or morefurther outputs. For example, in various embodiments, the electronicconverter comprises a further output terminal configured to provide afurther regulated voltage, wherein the further regulated voltage isreferred to the second input terminal, which represents a ground. Afurther capacitor is connected between the further output terminal andthe second input terminal, wherein a further electronic switch isconnected between the second terminal of the inductor and the furtheroutput terminal. In this case, the converter comprises also a fifthelectronic switch connected between the first terminal of the inductorand the second input terminal. Generally, the fifth electronic switchand/or the further electronic switch may be implemented with diodes.

In this case, the control circuit may thus also regulate the furtheroutput voltage. For example, during a further discharge phase, thecontrol circuit may close the fifth and the further electronic switch,whereby the current flowing through the inductor charges now the furthercapacitor, thereby increasing the voltage between the further outputterminal and the second input terminal. Similarly, the control circuitmay regulate the duration of the charge phase and/or the furtherdischarge phase, such that the voltage between the further outputterminal and the second input terminal corresponds to a furtherrequested value.

For example, in various embodiments, the control circuit is configuredfor repeating periodically the charge phase, the discharge phase and thefurther discharge phase, wherein one of the discharge phases correspondsto a last discharge phase and the other of the discharge phasescorresponds to an intermediate discharge phase between the charge phaseand the last discharge phase.

In this case, the control circuit may stop the intermediate dischargephase when the respective voltage being increased during theintermediate discharge phase reaches the respective requested value.Moreover, the control circuit may increase the duration of the chargephase when, at the end of the last discharge phase, the respectivevoltage being increased during the last discharge phase is smaller thanthe respective requested value, and decrease the duration of the chargephase when, at the end of the last discharge phase, the respectivevoltage being increased during the last discharge phase is greater thanthe respective requested value.

Generally, the electronic converter may also control the offset of thevoltage between the two output terminals with respect to the secondinput terminal, i.e., with respect to ground.

For example, in various embodiments, the electronic converter comprisesa reference voltage generator, such as a voltage divider, configured togenerate a reference voltage being preferably proportional to the supplyvoltage. In this case, a first resistor may be connected between thefirst output terminal and the reference voltage, and a second resistormay be connected between the second output terminal and the referencevoltage.

In various embodiments, the electronic converter may also be configuredto filter parasitic current spikes. For this purpose, the electronicconverter may comprise a first capacitor connected between the firstoutput terminal, and the first input terminal or the second inputterminal. Additionally or alternatively, the electronic converter maycomprise a second capacitor connected between the second outputterminal, and the first input terminal or the second input terminal.

Generally, in addition or as alternative to the coupling to thereference voltage, the converter may also comprise clamp circuits forlimiting the voltage offset of the two output terminals with respect tothe second input terminal, i.e., with respect to ground. Specifically,the electronic converter may comprise a first clamp circuit configuredto selectively permit a current flow towards the first output terminal,until the voltage between the first output terminal and the second inputterminal reaches or is greater than an upper voltage. The electronicconverter may comprise also a second clamp circuit configured toselectively permit a current flow from the second output terminal, untilthe voltage between the second output terminal and the second inputterminal reaches or is smaller than a lower voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will now be described withreference to the annexed drawings, which are provided purely by way ofnon-limiting example and in which:

FIGS. 1-4 have already been described in the foregoing;

FIG. 5 shows an embodiment of an electronic converter configured togenerate a regulated voltage in accordance with the present disclosure;

FIG. 6 shows an exemplary waveform of the regulated voltage generated bythe electronic converter of FIG. 5;

FIG. 7 shows a first embodiment of the electronic converter of FIG. 5;

FIG. 8 shows an embodiment of a control circuit of the electronicconverter of FIG. 7;

FIGS. 9A and 9B show possible switching states of the electronicconverter of FIG. 7;

FIG. 10 shows a waveform of the behavior of the electronic converter ofFIG. 7;

FIG. 11 shows a second embodiment of the electronic converter of FIG. 5;

FIG. 12 shows an embodiment of a control circuit of the electronicconverter of FIG. 11;

FIG. 13 shows a waveform of the behavior of the electronic converter ofFIG. 11;

FIGS. 14A, 14B and 14C show possible switching states of the electronicconverter of FIG. 11;

FIG. 15 shows a third embodiment of the electronic converter of FIG. 5;

FIG. 16 shows an embodiment of a reference voltage generator for theelectronic converter of FIG. 15;

FIG. 17 show details of the parasitic behaviors of the electronicconverter of FIG. 15;

FIG. 18 shows a fourth embodiment of the electronic converter of FIG. 5;

FIG. 19 shows a fifth embodiment of the electronic converter of FIG. 5;

FIGS. 20 and 21 show embodiments of clamp circuits for the electronicconverter of FIG. 19;

FIG. 22 shows an embodiment of a control circuit for the electronicconverters of FIGS. 11, 15, 18 and 19; and

FIG. 23 shows a sixth embodiment of the electronic converter of FIG. 5.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In the following description, numerous specific details are given toprovide a thorough understanding of embodiments. The embodiments can bepracticed without one or several specific details, or with othermethods, components, materials, etc. In other instances, well-knownstructures, materials, or operations are not shown or described indetail to avoid obscuring aspects of the embodiments.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment. Thus, the appearances of the phrases “in oneembodiment” or “in an embodiment” in various places throughout thisspecification are not necessarily all referring to the same embodiment.Furthermore, the particular features, structures, or characteristics maybe combined in any suitable manner in one or more embodiments.

The headings provided herein are for convenience only and do notinterpret the scope or meaning of the embodiments.

In the following FIGS. 5 to 23, parts, elements or components which havealready been described with reference to FIGS. 1 to 4 are denoted by thesame references previously used in such Figures. The description of suchpreviously described elements will not be repeated in the following inorder not to overburden the present detailed description.

As mentioned before, various embodiments of the present applicationrelate to an electronic converter, such as electronic converter 30 a foran audio system (see also the description of FIGS. 1 to 4).

FIG. 5 shows the general architecture of an embodiment of the electronicconverter 30 a. Generally, the electronic converter 30 a comprises twoinput terminals 300 and 302 for connection to a DC supply voltageV_(bat), where the negative terminal 302 represent a ground GND. Forexample, the terminals 300 and 302 may be connected to a battery BAT,such as the battery of a vehicle, such as a car.

In the embodiment considered, the electronic converter 30 a comprises atleast two output terminals 304 and 306 for providing a regulated voltageV_(float), which may, e.g., be used to power one or more digital/analogcircuits, such as the signal generator 10, and/or the blocks 202, 206and/or the control circuit 2060 described in with respect to FIG. 2.

Specifically, in various embodiments, the voltage at the terminal 304 isnot connected directly to ground GND, i.e., the voltage V_(float−)between the (negative) terminal 304 and ground GND is not zero. However,the electronic converter 30 a is configured to generate a regulated andsubstantially constant voltage V_(float) between the terminals 304 and306, such as 1.8 VDC.

Specifically, in various applications it may be desirable that thevoltage V_(float) is referred to a reference voltage V_(ref), which issmaller than the voltage V_(bat), i.e.:0<V _(ref) <V _(bat)

Specifically, in various embodiments, the converter 30 a generates avoltage V_(float+) between the positive terminal 306 and ground GND,which corresponds to:V _(float+) =V _(ref) +V _(float)/2.and a voltage V_(float−) between the negative terminal 304 and groundGND which corresponds to:V _(float−) =V _(ref) −V _(float)/2whereby the voltage between the (positive) terminal 306 and the(negative) terminal 304 corresponds to V_(float).

For example, in various embodiments, the reference voltage V_(ref) isvariable and set to 50% of the supply voltage V_(bat) (or generallyV_(ref)=x*V_(bat), with 0<x<1). For example, the reference voltageV_(ref) may be provided by an additional voltage regulator or a voltagedivider.

Generally, such a floating voltage V_(float) may be useful in manyapplications.

For example, in the case of an audio system, such a floating voltageV_(float) may be used by the analog circuits, in particular by thecircuit 2060, in order to improve the quality of the audio signal, inparticular with respect to the signal/noise ratio. For example, thissimplifies the implementation of unity-gain amplifier (as described,e.g., in documents Maxim, “APPLICATION NOTE 3977—Class D Amplifiers:Fundamentals of Operation and Recent Developments”, Jan. 31, 2007,available athttps://www.maximintegrated.com/en/app-notes/index.mvp/id/3977, or U.S.Pat. No. 8,558,618 B2, which are incorporated herein by reference)because the voltage gain of the amplifier stage 206 is unitary.Similarly, also the digital circuits may work with the floating voltageV_(float) in order to simplify the interface between the digital andanalog circuits.

For example, FIG. 6 shows exemplary waveform for the supply voltageV_(bat), the reference voltage V_(ref) and the voltages V_(float+) andV_(float−) (referred to ground GND).

As mentioned before, in case the converter 30 a is powered via a vehiclebattery BAT, the variation of the supply voltage V_(bat) may be fast (<2ms). In various embodiments, the converter 30 a should thus be able togenerate voltages V_(float+) and V_(float−) following such voltagevariations. For example, this implies that the capacitances associatedwith the terminals 304 and 306 with respect to ground GND should besmall.

In various embodiments (see, e.g., FIG. 5), the electronic converter 30a may also comprise one or more additional output terminals, such asterminals 308 and 310, for providing one or more additional supplyvoltages, such as voltages V₁ and V₂, which, e.g., may be used to powerthe driver circuits 2062 and 2054 arranged to drive the switches of ahalf-bridge. Generally, only a single terminal may be required for thesevoltages V₁ and V₂, insofar as these voltages may be referred to groundGND.

Accordingly, in various embodiments, the converter 30 a receives atinput a variable input voltage V_(bat) and provides at output one ormore voltages, which generally may be smaller or greater than the inputvoltage V_(bat). Thus, generally, a plurality of electronic convertersmay be used, wherein each electronic converter is configured to generatea respective one of the voltages V_(float+), V_(float−), V₁ and V₂.

Conversely FIG. 7 shows an embodiment of an electronic converter 30 aconfigured to generate a plurality of the voltages V_(float+),V_(float−), V₁ and V₂.

Specifically, in the embodiment considered, a so called Single-InductorMultiple-Output (SIMO) architecture is used. As the term implies, inthis case, the electronic converter 30 a comprises a single inductor L.

Specifically, in the embodiment considered, the electronic converter 30a comprise a half-bridge comprising two electronic switches Sh and Sl,such as (e.g., n-channel) FETs, connected (e.g., directly) in seriesbetween the terminals 300 and 302 arranged to receive the supply voltageV_(bat), i.e., the terminals 300 and 302 may be connected (directly orvia a cable) to the battery BAT.

In the embodiment considered, a first terminal of the inductor L isconnected (e.g., directly) to the intermediate point between theswitches Sl and Sh. The second terminal of the inductor L is connected(e.g., directly) via a further electronic switch Sbb to the negativeterminal 302. Moreover, the second terminal of the inductor L is alsoconnected (e.g., directly) via a respective switch, such as a (e.g.,n-channel) FET, to each of the output terminals of the electronicconverter 30 a, i.e., the terminals 304, 306 and the optional terminals308 and/or 310 For example, in the embodiment considered, the electronicconverter 30 a comprises:

an electronic switch S− connected (e.g., directly) between the secondterminal of the inductor L and the terminal 304 providing the voltageV_(float−);

an electronic switch S+ connected (e.g., directly) between the secondterminal of the inductor L and the terminal 306 providing the voltageV_(float+);

optionally an electronic switch S1 connected (e.g., directly) betweenthe second terminal of the inductor L and the terminal 306 providing thevoltage V₁; and

optionally an electronic switch S2 connected (e.g., directly) betweenthe second terminal of the inductor L and the terminal 308 providing thevoltage V₂.

In various embodiments, each of the switches S−, S+, S1 and S2 mayensure that current may flow form the second inductor terminal towardsthe respective output terminal. For this purpose, each of the switchesmay be:

a bidirectional switch, e.g., by using two field effect transistorsconnected in opposite direction in series, e.g., in case of n-channelFET the drain of a first FET may be connected to the second inductorterminal, the drain of a second FET may be connected to the respectiveoutput terminal, and the source terminals of the two FETs may beconnected together; or

an unidirectional switch, e.g., by connecting a diode in series with aFET.

Moreover, as will be described in the following, the electronic switchassociated with the output terminal 304, 306, etc., providing thehighest output voltage (e.g., switch S2 associated with the terminal 310providing the voltage V₂ to the driver circuit 2062) may also beimplemented with a diode.

In the embodiment considered, a respective capacitor C+, C−, C1 and C2is associated with each of the output terminals. Specifically, in theembodiment considered, each terminal 304, 306, 308 and 310 is connected(e.g., directly) via the respective capacitor C+, C−, C1 or C2 to groundGND.

As shown in FIG. 8, the electronic converter 30 a comprises also acontrol circuit 32 configured to generate drive signals DRVh, DRVl,DRVbb, DRV−, DRV+, DRV1 and DRV2 configured to drive the switches Sh,Sl, Sbb, S−, S+, S1 and S2, respectively, as a function of the outputvoltages V_(float−), V_(float+), V₁ and V₂, and the respective requestedoutput voltages (not shown in FIG. 8).

Generally, by driving the switches in an appropriate manner, theconverter 30 a may be operated as buck (step-down), boost (step-up) orbuck-boost converter.

For example, at the example of FIGS. 9A, 9B and 10 will be described apossible operation of the control circuit 32. Specifically, FIGS. 9A and9B show two exemplary switching states of the converter of FIG. 7. FIG.10 shows a possible waveform of the current I_(L) flowing through theinductor L.

In the embodiment considered, the control circuit 32 closes at aninstant t₀ and for a charge time T_(charge) the switches Sh and Sbb andmaintains opened the other switches (see FIG. 9A). Accordingly, duringthis phase the inductor L is connected to the supply voltage V_(bat) andthe current I_(L) increase substantially linearly.

At the end of the charge interval T_(charge), i.e., at an instant t₁,the control circuit 32 opened the switches Sh and Sbb, and closes theswitch Sl and one of the output switches S+, S−, S1 or S2 associatedwith the outputs, such as the switch S− (see FIG. 9B). Accordingly,during a following time interval T− the inductor current I_(L) flows tothe output 304 and the voltage V_(float−) increase, while the currentI_(L) decrease substantially linearly.

At an instant t₂, e.g., when the voltage V_(float−) has reached therequested value, the control circuit 32 opened the previously closedoutput switch, e.g., the switch S−, and closes a next output switch,such as the switch S+. Accordingly, during a following time interval T₊the inductor current I_(L) flows to the output 306 and the voltageV_(float+) increase, while the current I_(L) decrease substantiallylinearly.

At an instant t₃, e.g., when the voltage V_(float+) has reached therequested value, the control circuit 32 opened the previously closedoutput switch, e.g., the switch S+, and closes a next output switch,such as the switch S1. Accordingly, during a following time interval T₁the inductor current I_(L) flows to the output 308 and the voltage V₁increase, while the current I_(L) decrease substantially linearly.

At an instant t₄, e.g., when the voltage V₁ has reached the requestedvalue, the control circuit 32 opened the previously closed outputswitch, e.g., the switch S1, and closes a next output switch, such asthe switch S2. Accordingly, during a following time interval T₂ theinductor current I_(L) flows to the output 310 and the voltage V₂increase, while the current I_(L) decrease substantially linearly.

At an instant t₅, e.g., when the voltage V₂ has reached the requestedvalue, the control circuit 32 opened the previously closed outputswitch, e.g., the switch S2.

Generally, the sequence of the various discharge phases T₊, T⁻, T₁, andT₂ may also be different, and the converter may use more or less phasesin order to provide more or less output voltages.

The control circuit 32 may start a new cycle T_(charge) at a fixedfrequency or immediately with the instant t₅. The former being usuallyreferred to as Pulse Width Modulation (PWM) mode, while the latter isusually called quasi resonant mode.

Specifically, in various embodiments, apart from regulating thedurations of the various discharge phases, the control circuit 32 alsoregulates the duration of the charge phase T_(charge) in order to ensurethat sufficient energy is stored in the inductor L in order to reach therequested output voltages. For example, the control circuit 32 may usefor this purpose the voltage at the output terminal corresponding to thelast discharge phase, e.g., the voltage V₂ terminal 310.

For example, the control circuit 32 may increase the duration of thecharge phase T_(charge) when:

the inductor current I_(L) reaches zero and the voltage is smaller thanthe requested value, or

a new switching cycle starts with fixed frequency and the voltage issmaller than the requested value.

Similarly, the control circuit 32 may decrease the duration of thecharge phase T_(charge) when:

the voltage reaches the requested value and the inductor current I_(L)is greater than zero, or in a complementary manner the inductor currentI_(L) reaches zero and the voltage is greater than the requested value,or

a new switching cycle starts with fixed frequency and the voltage isgreater than the requested value.

Thus, in the embodiment considered, the control circuit 32 may use afixed reference values for the voltages V₁ and V₂, thereby providingsubstantially constant voltages V₁ and V₂. Conversely, the controlcircuit 32 may use variable reference values for the voltages V_(float+)and V_(float−) determined as a function of the voltage V_(bat), therebyproviding variable voltages V_(float+) and V_(float−), where the voltageV_(float) between the terminals 304 and 306 is substantially constant(as described in the foregoing).

Generally, instead of using a single charge phase T_(charge), theconverter may use also a plurality of charge phases, e.g., a respectivecharge phase for each discharge phase. For example, in this case, theelectronic converter 30 a may be operated as a buck-boost converter,where a plurality of outputs is regulated sequentially. Accordingly, inthe embodiment considered, the electronic converter 30 a is used in atime-sharing mode, where the switches Sh, Sl and Sbb and the inductor Lare sequentially used to provide power to one of the output capacitors(by closing one of the switches S−, S+, S1 or S2).

Again, as mentioned in the foregoing, the electronic converter 30 acould also generate only the voltages V_(float+) and V_(float−).Moreover, based on the values of the supply voltage V_(bat) and therequested output voltages, the control circuit 32 may operate theswitches in order to implement other converter topologies, which controlthe current flowing through the inductor L, such as:

a buck converter, where the switch Sbb remains opened, and the controlcircuit 32 closes alternatively the switches Sh and Sl, e.g., in orderto generate a voltage V₁ being smaller than the supply voltage V_(bat);and

a boost converter, where the switch Sh remains closed and the switch Slremains opened, and the control circuit 32 closes alternatively theswitch Sbb and, e.g., the switch S2 in order to generate a voltage V₂being greater than the supply voltage V_(bat).

In various embodiments, due to the fact that the voltages V_(float+) andV_(float−) are between the minimum and the maximum value of the supplyvoltage V_(bat), the control circuit 32 operates at least for thesevoltages the converter 30 a as buck-boost converter as described in theforegoing.

While the solution described in the foregoing is a valid solution inorder to generate constant or almost constant output voltage, e.g., thevoltages V₁ and V₂, the solution may present some drawbacks for thegeneration of variable voltages, such as the voltages V_(float+) andV_(float−). For example, as mentioned in the foregoing, the supplyvoltage V_(bat) and thus the reference voltage V_(ref) may vary fast (<2ms). Thus, the electronic converter 30 a should be able to provide alsovoltages V_(float+) and V_(float−), which are able to follow thesevariations. However, the architecture shown in FIG. 7 requires thetank/output capacitors C+ and C−, which are charged by the currentI_(L). Moreover, the converter is operated sequentially with thetime-sharing technique. Thus, the output capacitors may not be toosmall. For example, the capacitances of the capacitors C1 and C2 may bebetween 5 e 100 uF, e.g., approximately 10 uF. Thus, in order to followvariations having a frequency being greater than 100 Hz, large charge ordischarge currents would be required, which would render the system lessefficient.

Moreover, the voltages V_(float+) and V_(float−) are regulatedindependently, thereby using two separate control loops. These loopshave to ensure a sufficient precision in order to obtain the requestedvoltage V_(float).

FIG. 11 shows thus a second embodiment of the electronic converter 30 a.Specifically, in the embodiment considered, the electronic switch S−associated with the terminal 304 providing the voltage V_(float−) is notconnected anymore to the second terminal of the inductor L, but to thefirst terminal of the inductor L, i.e., the intermediate point betweenthe switches Sh and Sl of the half-bridge. Moreover, a single capacitorCf is connected between the terminals 304 and 306. In some embodiments,the capacitors C+ and C− are preferably omitted.

FIG. 13 shows again a possible waveform of the current I_(L) flowingthrough the inductor L, and FIGS. 14a, 14b and 14c show variousswitching stages of the converter 30 a.

Specifically, the control circuit 32 closes again at an instant t₀ andfor a charge time T_(charge) the switches Sh and Sbb and maintainsopened the other switches (see FIG. 14A). Accordingly, during this phasethe current I_(L) increase substantially linearly. At an instant t₁, thecontrol circuit 32 opens thus the switches Sh and Sbb and the chargephase ends.

During the following discharge phases, the energy stored in the inductorL is then provided to the output terminals. Specifically, during one ofthe discharge phases T_(+/−), e.g., the first discharge phase, thecontrol circuit 32 drives the control terminal of the switches S+ and S−in order to close these switches, e.g., at the instant t₁ (see FIG.14B). Accordingly, in this embodiment, the switches S+ and S− are closedduring the same phase. As shown in FIG. 12, the control circuit 32 maythus generate (in addition to the drive signals DRVh, DRVl, DRVbb, DRV1and DRV2 configured to drive the switches Sh, Sl, Sbb, S1 and S2,respectively) a common drive signal DRVf, which drives simultaneouslythe switches S+ and S−. Moreover, as shown in FIG. 12, in the embodimentconsidered, the control circuit 32 receives at input directly thevoltage difference V_(float).

Specifically, when both switches S+ and S− are closed, the inductorcurrent I_(L) will flow from the terminal 304 to the terminal 306,thereby charging the capacitor Cf. Thus, the voltage V_(float−) willdecrease and the voltage V_(float−) will increase, whereby the V_(float)between the terminals 304 and 306 will increase. Thus, in the embodimentconsidered, the current I_(L) decrease substantially linearly and thecontrol circuit 32 may switch off the switches S+ and S− at an instantt₃ directly when the voltage V_(float) reaches the requested constantvalue. Generally, in case unidirectional switches are used for theswitches S+ and S−, these switches should support the mentioned currentflow direction, i.e., the switch S− should be configured to permit acurrent flow from the terminal 304 towards the first terminal of theinductor L (as a function of the respective drive signal DRV−/DRVf) andthe switch S+ should be configured to permit a current flow from thesecond terminal of the inductor L towards the terminal 306 (as afunction of the respective drive signal DRV+/DRVf).

Thus, at the instant t₃, the control circuit 32 opened the previouslyclosed output switches S+ and S−, and closes the switch Sl and one ofthe other output switches, such as the switch S1 (see FIG. 14C).Accordingly, as in the previous embodiment, during a following timeinterval T₁ the inductor current I_(L) flows now from ground GND (viathe switches Sl an S1) to the output 308 and the voltage V₁ increase,while the current I_(L) decrease substantially linearly.

At an instant t₄, e.g., when the voltage V₁ has reached the requestedvalue, the control circuit 32 opened the previously closed outputswitch, e.g., the switch S1, and closes a next output switch, such asthe switch S2. Accordingly, during a following time interval T₂ theinductor current I_(L) flows to the output 310 and the voltage V₂increase, while the current I_(L) decrease substantially linearly.

At an instant t₅, e.g., when the voltage V₂ has reached the requestedvalue, the control circuit 32 opened the previously closed outputswitch, e.g., the switch S2.

Again, the sequence of the various discharge phases T_(+/−), T₁, and T₂may also be different, and the converter may use more or less phases inorder to provide more or less output voltages. Moreover, also in thiscase, a plurality of charge phase may be used, such as a respectivecharge phase for each discharge phase.

Thus, in the embodiment considered, during one of the discharge phases,both switches S+ and S− are closed (while the other switches Sh, Sl,Sbb, S1 and S2 are opened). Thus, in the embodiment considered, theinductor current I_(L) charges the capacitor Cf and the control circuitmay directly regulate the output voltage V_(float).

Again, considering the voltage levels at the inductor L, the switch Sland/or the switch connected to the output terminal providing the highestoutput voltage (e.g., the switch S2) may also be implemented with adiode, and the control unit 302 may thus not generate the respectivedrive signals, e.g., the drive signal DRVl for the switch Sl and thedrive signal DRV2 for the switch S2.

In the embodiment shown in FIGS. 11 and 12, the control circuit 32regulates only the voltage difference between the terminals 304 and 306,i.e., the voltage V_(float). However, the control circuit 32 does notregulate the offset of the voltages V_(float+) and V_(float−) withrespect to ground GND.

Generally, the control circuit 32 could thus also regulate the voltagesV_(float+) and V_(float−) with respect to ground GND. For example, in anembodiment, the control circuit 32 could close both switches S+ and S−until either the voltage V_(float+) or the voltage V_(float−) reachesthe requested reference value (V_(ref)+/−V_(float)/2), and then either:

when the voltage V_(float+) has reached the requested voltage(V_(ref)+V_(float)/2), continue to discharge the terminal 302 towardsground GND (e.g., by closing the switch Sbb) or towards one of the otheroutput terminals (e.g., via the switch S1 or S2); or

when the voltage V_(float−) has reached the requested voltage(V_(ref)−V_(float)/2), continue to charge the terminal 304 from groundGND e.g., by opening the switch S− and closing the switch Sl.

Unfortunately, this control is rather complex and instead of using asingle capacitor Cf, two capacitors C+ and C− would again be required.Substantially, in this case, the voltages V_(float+) and V_(float−)would have to be regulated again individually, with the associatedcomplexity to obtain the requested variable values.

FIG. 15 shows an embodiment, which permits a simplified control ofvoltage offset of the voltages V_(float+) and V_(float−). Specifically,in the embodiment considered, the control circuit 32 regulates theduration of the interval T_(+/−) in order to obtain the requestedvoltage difference V_(float) (as described with respect to FIGS. 11-14),however, the control circuit 32 does not regulate the voltage V_(float+)and V_(float−) with respect to ground GND. Conversely, the offset ofthese voltages V_(float+) and V_(float−) is imposed separately bycoupling the terminals 302 and 304 to the reference voltage V_(ref),representing a common mode for the terminals 302 and 304.

In various embodiments (see FIG. 16), the converter 30 a may thuscomprise a circuit 34 configured to generate the voltage V_(ref) at anode/terminal 312 as a function of the voltage V_(bat). For example, invarious embodiments, the circuit 34 comprises a resistive voltagedivider comprising two resistors R_(ref1) and R_(ref2) connected (e.g.,directly) between the terminals 300 and 302. Accordingly, in theembodiment considered, the voltage V_(ref) at the intermediate pointbetween the two resistors R_(ref1) and R_(ref2) (representing thenode/terminal 312 in the embodiment considered) will be proportional tothe supply voltage V_(bat) based on the values of the resistors R_(ref1)and R_(ref2). For example, in various embodiments, the resistorsR_(ref1) and R_(ref2) have substantially the same value. Generally, thecircuit 34 may also comprise more complex circuits for implementing areference voltage generator, possibly comprising also amplifier stages(such as one or more operation amplifiers and/or current mirrors) inorder to ensure a stable output voltage V_(ref) for different loadconditions at the node/terminal 312.

In the embodiments considered, the terminals 304 and 306 are coupled tothe voltage V_(ref) via respective resistors Rcm1 and Rcm2, i.e., aresistor Rcm1 is connected (e.g., directly) between the terminal 306 andthe terminal 312 providing the voltage V_(ref) (e.g., the intermediatepoint between the resistors Rref1 and Rref2) and a resistor Rcm2 isconnected (e.g., directly) between the terminal 304 and the terminal312. In order to obtain the voltages V_(ref)+/−V_(float)/2 the resistorsRcm1 and Rcm2 should have the same value. However, generally theresistors could also have different values, e.g., when a differentscaling with respect to the ground GND is requested.

For example, assuming a switching frequency of 2 MHz, the inductance ofthe inductor L may be 10 μH, the capacitance of the capacitor Cf may be10 μF, the resistances of the resistors Rcm1 and Rcm2 may be 10 kΩ, andthe resistances of the resistors Rref1 and Rref2 may be 10 kΩ.Accordingly, typically the inductor L, the capacitor Cf and theresistors Rcm1, Rcm2, Rref1 and Rref2 have values in the micro-henry(μH)/micro-farad (μF)/kilo-ohm (kΩ) range, respectively.

The inventors have observed that the solution described with respect toFIGS. 15 and 16 is a valid solution, in particular when no highprecision of the offsets V_(float+) and V_(float−) with respect to theground GND is required. From a practical point of view, the circuitwill, however, comprise also parasitic capacitance, such as capacitancesassociated with the first and second terminal of the inductor L.

For example, this is shown in FIG. 17, wherein parasitic currentsI_(par1) and I_(par2) are flowing through the switches S+ and S−,respectively. Specifically, these parasitic currents I_(par1) andI_(par2) do not flow through the inductor L but towards the positivesupply voltage V_(bat) and/or ground GND. The inventors have observedthat (based on the implementation of the switches S+ and S−) usuallythese parasitic current I_(par1) and I_(par2) flow only during a briefinterval at the instant t₁ when the switches S+ and S− are closed, i.e.,the duration of the current pulses is significantly smaller than theduration of the interval T_(+/−). In principle, these parasitic currentsI_(par1) and I_(par2) would not represent any particular issue, whentheir amplitude would be the same. However, in case the values aredifferent, a current (I_(par1)−I_(par2)) will also flow towards the node312 providing the reference voltage V_(ref). For example, in case thereference voltage V_(ref) is provided by a voltage divider (see FIG.16), this current will vary the reference voltage V_(ref) from therequested value.

FIG. 18 shows thus a modified embodiment that is capable of inhibitingor at least reducing this current flow towards the node 312.Specifically, in the embodiment considered, the electronic converter 30a comprises (in addition to the components described with respect toFIG. 15) at least one of:

a capacitor Cf1 connected (e.g., directly) between the terminal 306 andthe terminal 300 providing the supply voltage V_(bat); and

a capacitor Cf2 connected (e.g., directly) between the terminal 304 andground GND, i.e., the terminal 302.

In various embodiments, taking into account typical values for theparasitic current I_(par1) and I_(par2) the capacitors Cf1 and Cf2 mayhave a capacitance being significantly smaller than the capacitance ofthe capacitor Cf, such as less than 5%, preferably between 0.1% and 2%,preferably approximately 1%. For example, in various embodiments, thecapacitance of the capacitors Cf1 and Cf2 is between 10 and 100 nF. Invarious embodiments, the capacitors Cf1 and Cf2 may have the samecapacitance.

Accordingly, in the embodiment considered, the parasitic currentsI_(par1) and I_(par2) will also flow. However, the current pulse(I_(par1)−I_(par2)) will not flow (or will flow less) towards the node312 but through the low impedance path provided by the capacitor Cf1and/or the capacitor Cf2 (and also the capacitor Cf).

Generally, the capacitors Cf1 and/or Cf2 may be connected to anyreference voltage having a low impedance towards ground GND (as it isthe case for the supply voltage V_(bat)). For example, the capacitorsCf1 may also be connected to the terminal 302 (instead of the terminal300) and/or the capacitors Cf2 may also be connected to the terminal 300(instead of the terminal 302).

FIG. 19 shows a second embodiment for obtaining the voltage offsetsV_(float+) and V_(float−) with respect to ground GND. Specifically, theembodiment is based on the circuit shown in FIG. 11 and comprises inaddition two further circuits:

a first clamp circuit 36 connected (e.g., directly) to the terminal 306;and

a second clamp circuit 38 connected (e.g., directly) to the terminal308.

Specifically, in the embodiment considered, the first clamp circuit 36is configured to selectively permit a current flow towards the terminal306 until the voltage corresponds to an upper voltage threshold V_(H).

For example, as shown in FIG. 20, the clamp circuit 36 may comprise atransistor 362, such as a n-channel FET, such as an NMOS, connected(e.g., directly) between the terminal 300 providing the supply voltageV_(bat) and the terminal 306.

In the embodiment considered, the gate terminal of the transistor 362 isdriven by an operational amplifier 364. Specifically, in the embodimentconsidered, the operational amplifier 364 receives at thenon-inverting/positive input terminal the upper voltage threshold V_(H)and at the inverting/negative input terminal the voltage at the terminal306.

Accordingly, the circuit 36 will drive the transistor 362 therebypermitting a current flow (from the supply voltage V_(bat)) towards theterminal 306, until the voltage at the terminal 306 reaches or isgreater than the voltage V_(H).

Conversely, in the embodiment considered, the second clamp circuit 38 isconfigured to selectively permit a current flow from the terminal 304until the voltage corresponds to a lower voltage threshold V_(L).

For example, as shown in FIG. 21, the clamp circuit 38 may comprise atransistor 382, such as a p-channel FET, such as a PMOS, connected(e.g., directly) between the terminal 304 and the terminal 302 (groundGND).

In the embodiment considered, the gate terminal of the transistor 382 isdriven by an operational amplifier 384. Specifically, in the embodimentconsidered, the operational amplifier receives at thenon-inverting/positive input terminal the lower voltage threshold V_(L)and at the inverting/negative input terminal the voltage at the terminal304.

Accordingly, the circuit 38 will drive the transistor 382 therebypermitting a current flow from the terminal 304 (towards ground GND),until the voltage at the terminal 304 reaches or is smaller than thevoltage V_(L).

In various embodiments, the clamp circuits 36 and 38 are not used todirectly impose the voltages V_(ref)+/−V_(float)/2, but the clampcircuits set only approximately the voltages at the nodes 304 and 306with respect to ground GND.

Specifically, in various embodiments, the upper and the lower thresholdcorrespond to:V _(H) =V _(ref) +V _(float)/2−ΔV _(L) =V _(ref) −V _(float)/2+Δ

Accordingly, without any switching activity of the switches Sh, Sl, Sbb,the clamp circuits 36 and 38 would set the following voltages (via thecoupling of the capacitor Cf):V _(float+) =V _(ref) +V _(float)/2−ΔV _(float−) =V _(ref) −V _(float)/2+Δand the voltage difference V_(Diff) between the terminals 306 and 304would be:V _(Diff+) F=V _(float)−2Δ

For example, in various embodiments, the value of Δ is selected between5% and 20% of the value of V_(float), e.g., Δ=0.1 V_(float). Forexample, Δ may be between 150 and 180 mV for V_(float)=1.8 V.

Accordingly, once the control unit 32 drives the switches of theconverter 30 a, the control unit 32 will also regulate the voltagedifference V_(Diff) until the value corresponds to the requested valueV_(float).

When the supply voltage V_(bat) remains constant, the clamp circuits 36and 38 do not intervene during this regulation of the voltage differenceV_(Diff). Conversely, the clamp circuits 34 and 36 may absorb thecurrent peaks generated by the parasitic current mentioned before and/ormay intervene when the supply voltage V_(bat) varies.

FIG. 22 shows in this respect a possible embodiment of the controlcircuit 32. Specifically, in the embodiment considered, the voltagesV_(float+) and V_(float−) are provided to a differential amplifier 320,e.g., based on an operation amplifier. The output of the differentialamplifier 320 is connected to an error amplifier 324, such as a PI(Proportional-Integral) or PID (Proportional-Integral-Derivative)regulator, configured to generate an error signal as a function of thevoltage difference and a reference signal REF. In the embodimentconsidered a scaling circuit and/or a current-voltage conversion circuit322, such as a voltage divider comprising two resistors, may beconnected between the differential amplifier 320 and the error amplifier324.

In the embodiment considered, the optional voltages V₁ and V₂ may beprovided similarly to respective error amplifiers 332 and 336. Whilealso in this case may be used scaling circuits 330 and 334, usually nodifferential amplifiers are required, because the voltages V₁ and V₂ arereferred to ground GND.

The error signals at the output of the error amplifiers 324, 332 and 336are provided to a driver circuit 326. Specifically, in the embodimentconsidered, the driver circuit 326 is configured to manage the chargephase and the various discharge phases by generating the drive signalsfor the switches Sh, Sl, Sbb, S+, S− S1 and S2. Generally, the drivesignal DRVl for the switch Sl and the drive signal DRV2 for the switchS2 are purely optional, because these switches may also be implementedwith diodes.

For example, in various embodiments, the driver circuit 326 may be aPulse-Width-Modulation (PWM) driver circuit. For this reason, the drivercircuit 326 may have associated an oscillator 328 configured to generatean oscillator signal having a fixed frequency, i.e., a fixed switchingperiod T_(SW).

For example, once the oscillator signal indicates the start of a newswitching cycle (corresponding essential to the instant t₀ of FIG. 13),the driver circuit 326 sets the drive signals DRVh and DRVbb for closingthe switches Sh and Sbb. At the instant t₁, i.e., after the durationT_(charge), the driver circuit 326 sets the drive signals DRVh and DRVbbfor opening the switches Sh and Sbb. Accordingly, in the embodimentconsidered, these drive signals DRVh and DRVbb are PWM signals, whichare set:

to a first logic level (e.g., high) for a switch-on durationcorresponding to the duration T_(charge); and

to a second logic level (e.g., low) for a switch-off durationcorresponding to T_(SW)−T_(charge).

In the embodiment considered, the driver circuit 326 sets then (e.g., atthe instant t₁) the drive signal DRVf for closing the switches S+ andS−. At the instant t₃, i.e., after the duration T_(+/−), the drivercircuit 326 sets the drive signal DRVf for opening the switches S+ andS−. Accordingly, in the embodiment considered, the drive signal DRVf isa PWM signal, which is set:

to a first logic level (e.g., high) for a switch-on durationcorresponding to the duration T_(+/−); and

to a second logic level (e.g., low) for a switch-off durationcorresponding to T_(SW)−T_(+/−).

In the embodiment considered, the driver circuit 326 sets then (e.g., atthe instant t₃) the drive signal DRV1 for closing the switch S1 (andpossibly the drive signal DRVl for closing the switch Sl). At theinstant t₄, i.e., after the duration T₁, the driver circuit 326 sets thedrive signal DRV1 for opening the switch S1. Accordingly, in theembodiment considered, the drive signal DRV1 is a PWM signal, which isset:

to a first logic level (e.g., high) for a switch-on durationcorresponding to the duration T₁; and

to a second logic level (e.g., low) for a switch-off durationcorresponding to T_(SW)−T₁.

Generally, the driver circuit 326 may then generate the drive signalDRV2 for the switch S2. Conversely, in the embodiment considered theswitch S2 is implemented with a diode. Accordingly, when the switchesS+, S− and S1 are opened, the current I_(L) will flow through the diodeS2 towards the terminal 310 until the current I_(L) reaches zero or theswitching duration T_(SW) has finished.

Specifically, in the embodiment considered, the driver circuit 326 isconfigured to vary the switch-on durations T_(+/−) and T₁ of the drivesignals DRVf and DRV1 as a function of the error signals provided by theerror amplifiers 324 and 332, respectively. Specifically, in theembodiment considered, the error amplifiers 324 and 332 will vary thesedurations (via the respective error signals) until the voltagesV_(float) and V₁ correspond to the respective requested values.

Conversely, in the embodiment considered, the driver circuit 326 isconfigured to vary the switch-on duration T_(charge) of the drivesignals DRVh and DRVbb as a function of the error signal provided by theerror amplifiers 336. Specifically, in the embodiment considered, theerror amplifier 336 will vary the duration (via the respective errorsignal), thereby varying the maximum current I_(L), until the voltagesV₂ correspond to the respective requested values. Additionally, thedriver circuit 326 may vary the switch-on duration T_(charge) also as afunction of the error signals provided by the other error amplifiers,e.g., the amplifiers 324 and 332, which may be useful in order toperform a (predictive) control in case of short load variations of theoutputs. For example, such an arrangement is useful when the erroramplifiers 324, 332 and 336 have (in addition to an integral component)a proportional and/or derivative component.

Accordingly, in various embodiments, the control unit 32 is configuredto manage the following phases which are repeated periodically:

a charge phase T_(charge), wherein the control circuit 32 closes theswitches Sh and Sbb for storing energy in the inductor L;

a (last) discharge phase, wherein the energy stored in the inductor L istransferred to an output; and

one or more optional intermediate discharge phases between the chargephase and the last discharge phase, wherein the energy stored in theinductor L is transferred to one or more respective other outputs.

Generally, the discharge phase T_(+/−) may be the last discharge phaseor an intermediate discharge phase.

Specifically, in various embodiments, the control unit is configured tostop an intermediate phase when the respective output voltage reachesthe requested value. Conversely, the last discharge phase is used tocontrol the duration of the charge phase T_(charge).

For example, by using a PWM modulation with constant switching cycleT_(SW), the control unit 32 may:

increase the duration of the charge phase T_(charge) (while maintainingthe total duration T_(SW)) when, at the end of the last discharge phase,the respective output voltage is smaller than the requested value; and

decrease the duration of the charge phase T_(charge) (while maintainingthe total duration T_(SW)) when, at the end of the last discharge phase,the respective output voltage is greater than the requested value.

Generally, the duration of the last discharge phase may also beconstant. Thus, the control unit 32 may:

increase the duration of the charge phase T_(charge) when, at the end ofthe last discharge phase, the respective output voltage is smaller thanthe requested value; and

decrease the duration of the charge phase T_(charge) when, at the end ofthe last discharge phase, the respective output voltage is greater thanthe requested value.

Most of the components of the electronic converters 30 a described inthe foregoing may also be integrated in an integrated circuit.Generally, the term integrated circuit does not imply that the die ismounted within a package, but e.g., the die could also be mounteddirectly on a printed-circuit-board (PCB). Thus, the term pad is used toidentify the pad of the die of the integrated circuit and the term pinidentifies the pin or lead of an optional external package of theintegrated circuit. Thus, when using the term “pad/pin” this indicatesthat the die has a pad and in case an external package is used, also thepackage has a corresponding pin, which is connected to the respective

For example, FIG. 23 shows an embodiment, where such integrated circuitmay comprise:

two pins/pads 300 and 302 for connection to the supply voltage V_(bat);

the switches Sh, Sbb, S+ and S−;

the switch/diode Sl;

the optional switch S1;

the optional switch/diode S2;

the control circuit 32; and

the optional clamp circuits 36 and 38.

In various embodiments, the integrated circuit does not comprise largeinductors, capacitors and resistors, such as the inductor L, thecapacitor Cf, and the capacitors C1 and C2, i.e., these components areexternal with respect to the integrated circuit. Conversely, smallcapacitors, such as the capacitors Cf1 and Cf2, and the variousresistors described may be external or internal.

For example, in the embodiment considered, the integrated circuitcomprises:

two pins/pads 400 and 402 for connection to an external inductor L;

a pin/pad 308 for connection to an external capacitor C1 (being optionalinsofar as the voltage V₁ is optional);

a pin/pad 310 for connection to an external capacitor C2 (being optionalinsofar as the voltage V₂ is optional); and

at least two pins/pads for connection to the capacitor Cf.

Generally, the capacitor Cf may be connected directly to two pads/pins304 and 306. Conversely, FIG. 23 shows an embodiment where fourpins/pads 304, 306, 404 and 406 are used. Specifically, the pins/pads404 and 406 are connected directly to the switches S− and S+,respectively. Conversely, the pins/pads 304 and 306 provide the voltagesV_(float−) and V_(float+). Accordingly, in the embodiment considered, afirst terminal of an external capacitor Cf may be connected to thepins/pads 304 and 404, thereby connecting the pin/pad 304 externally tothe pin/pad 404, and a second terminal of the external capacitor Cf maybe connected to the pins/pads 306 and 406, thereby connecting thepin/pad 306 externally to the pin/pad 406.

Specifically, this embodiment has the advantage that the parasiticinductances Lbond1, Lbond2, Lbond3 and Lbond4 of the bonding of the pins304, 306, 404 and 404 implement with the capacitor Cf an improved filterstage for current peaks.

Generally, the various embodiments may also be combined. For example, inFIG. 23, the integrated circuit comprises also the clamp circuits 38 and36 which are connected internally to the pins/pads 306 and 304.

Moreover, in the embodiment considered, the electronic convertercomprises the capacitors Cf1 and Cf2, which are connected externally tothe pins/pads 304/404 and 306/406, respectively.

Similarly, the electronic converter could also comprise the couplingresistors Rcm1 and Rcm2, which may be connected externally in parallelto the capacitor Cf or internally between the pins/pads 304/306 or404/406.

Accordingly, the various embodiments described with respect to FIGS. 11to 23 have the following advantages:

only a single phase T_(−/−) is requested in order to regulate the outputvoltage V_(float); accordingly, only a single control loop may berequired, because only a single drive signal DRVf may be used;

a single output capacitor Cf is required for providing the outputvoltage V_(float); accordingly, except for the parasitic currents andthe optional filter capacitors Cf1 and CF2, the current used to chargethe output capacitor does not flow towards ground GND;

the offset voltages V_(float+) and V_(float−) may be regulated faster,because the capacitances of the respective terminals towards the supplyvoltage V_(bat) and ground GND are small.

Moreover, as described in the foregoing, the same electronic converter30 a may be used to generate in addition to the voltage V_(float) alsoone or more additional voltages V₁ and V₂. In case these voltages areabsent, the respective switches S1 and S2, and also the switch/diode S1may be omitted.

Of course, without prejudice to the principle of the invention, thedetails of construction and the embodiments may vary widely with respectto what has been described and illustrated herein purely by way ofexample, without thereby departing from the scope of the presentinvention, as defined by the ensuing claims.

What is claimed is:
 1. An electronic converter comprising: a first inputterminal and a second input terminal configured to receive a supplyvoltage across the first and second input terminals, wherein the secondinput terminal is configured to receive a ground voltage; a first outputterminal and a second output terminal configured to provide a regulatedvoltage across the first and second output terminals, wherein a firstfloating voltage at the first output terminal is configured to vary withrespect to the ground voltage while the first and second outputterminals provide the regulated voltage across the first and secondoutput terminals, the first and second output terminals configured to becoupled to a capacitor; a first inductor terminal and a second inductorterminal, the first and second inductor terminals configured to becoupled to an inductor; a first switch coupled between the first inputterminal and the first inductor terminal; a second switch coupledbetween the second inductor terminal and the second input terminal; athird switch coupled between the second inductor terminal and the firstoutput terminal; a fourth switch coupled between the first inductorterminal and the second output terminal; and a control circuitconfigured to: monitor the regulated voltage, during a charge phase,increase an inductor current flowing through the inductor by closing thefirst and second switches, during a discharge phase, increase theregulated voltage and charge the capacitor with the inductor current byclosing the third and fourth switches, and regulate a duration of thecharge phase or the discharge phase such that the regulated voltagecorresponds to a target value.
 2. The electronic converter of claim 1,wherein the control circuit is configured to: at an end of the dischargephase, compare the regulation voltage with the target value; increase aduration of the charge phase when the regulation voltage is smaller thanthe target value; and decrease the duration of the charge phase when theregulation voltage is greater than the target value.
 3. An electronicconverter comprising: a first input terminal and a second input terminalconfigured to receive a supply voltage across the first and second inputterminals; a first output terminal and a second output terminalconfigured to provide a regulated voltage across the first and secondoutput terminals, the first and second output terminals configured to becoupled to a capacitor; a first inductor terminal and a second inductorterminal, the first and second inductor terminals configured to becoupled to an inductor; a first switch coupled between the first inputterminal and the first inductor terminal; a second switch coupledbetween the second inductor terminal and the second input terminal; athird switch coupled between the second inductor terminal and the firstoutput terminal; a fourth switch coupled between the first inductorterminal and the second output terminal; a fifth switch coupled betweenthe first inductor terminal and the second input terminal; a thirdoutput terminal configured to provide a second regulated voltage withrespect to the second input terminal; a second capacitor coupled betweenthe second output terminal and the second input terminal; a sixth switchcoupled between the second inductor terminal and the third outputterminal; and a control circuit configured to: monitor the regulatedvoltage, during a charge phase, increase an inductor current flowingthrough the inductor by closing the first and second switches, during adischarge phase, increase the regulated voltage and charge the capacitorwith the inductor current by closing the third and fourth switches,regulate a duration of the charge phase or the discharge phase such thatthe regulated voltage corresponds to a target value, monitor the secondregulated voltage, during a second discharge phase, increase the secondregulated voltage and charge the second capacitor with the inductorcurrent by closing the fifth and sixth switches, and regulate theduration of the charge phase or the second discharge phase such that thesecond regulated voltage corresponds to a second target value.
 4. Theelectronic converter of claim 3, wherein the fifth switch or the sixthswitch is a diode.
 5. The electronic converter of claim 3, wherein thecontrol circuit is further configured to repeat periodically the chargephase, the discharge phase, and the second discharge phase, wherein oneof the discharge phase and the second discharge phase corresponds to alast discharge phase and the other of the discharge phase and the seconddischarge phase corresponds to an intermediate discharge phase betweenthe charge phase and the last discharge phase.
 6. The electronicconverter of claim 5, wherein the control circuit is further configuredto stop the intermediate discharge phase when a respective voltage beingincreased during the intermediate discharge phase reaches a respectivetarget value, wherein the respective voltage corresponds to theregulated voltage when the intermediate discharge phase corresponds tothe discharge phase and to the second regulated voltage when theintermediate discharge phase corresponds to the second discharge phase,and wherein the respective target value corresponds to the target valuewhen the intermediate discharge phase corresponds to the discharge phaseand to the second target value when the intermediate discharge phasecorresponds to the second discharge phase.
 7. The electronic converterof claim 5, wherein the control circuit is further configured to:increase the duration of the charge phase when, at an end of the lastdischarge phase, a respective voltage being increased during the lastdischarge phase is smaller than a respective target value; and decreasethe duration of the charge phase when, at the end of the last dischargephase, the respective voltage is greater than the respective targetvalue, wherein the respective voltage corresponds to the regulatedvoltage when the last discharge phase corresponds to the dischargephase, and to the second regulated voltage when the last discharge phasecorresponds to the second discharge phase and wherein the respectivetarget value corresponds to the target value when the last dischargephase corresponds to the discharge phase and to the second target valuewhen the last discharge phase corresponds to the second discharge phase.8. The electronic converter of claim 1, further comprising: a referencevoltage generator coupled between the first input terminal and thesecond input terminal, the reference voltage generator configured togenerate a reference voltage at a reference voltage node; a firstresistor coupled between the first output terminal and the referencevoltage node; and a second resistor coupled between the second outputterminal and the reference voltage node.
 9. The electronic converter ofclaim 8, wherein the reference voltage generator comprises a voltagedivider coupled between the first input terminal and the second inputterminal, and wherein the voltage divider comprises the referencevoltage node.
 10. The electronic converter of claim 8, wherein thereference voltage is proportional to the supply voltage.
 11. Theelectronic converter of claim 1, further comprising: a first capacitorcoupled between the first output terminal and the first input terminalor the second input terminal; or a second capacitor coupled between thesecond output terminal and the first input terminal or the second inputterminal.
 12. An electronic converter comprising: a first input terminaland a second input terminal configured to receive a supply voltageacross the first and second input terminals; a first output terminal anda second output terminal configured to provide a regulated voltageacross the first and second output terminals, the first and secondoutput terminals configured to be coupled to a capacitor; a firstinductor terminal and a second inductor terminal, the first and secondinductor terminals configured to be coupled to an inductor; a firstswitch coupled between the first input terminal and the first inductorterminal; a second switch coupled between the second inductor terminaland the second input terminal; a third switch coupled between the secondinductor terminal and the first output terminal; a fourth switch coupledbetween the first inductor terminal and the second output terminal; afirst clamp circuit configured to selectively permit a current flowtowards the first output terminal until a voltage between the firstoutput terminal and the second input terminal is greater than or equalto an upper voltage; a second clamp circuit configured to selectivelypermit a current flow from the second output terminal until a voltagebetween the second output terminal and the second input terminal is lessthan or equal to a lower voltage, wherein the upper voltage is higherthan the lower voltage; and a control circuit configured to: monitor theregulated voltage, during a charge phase, increase an inductor currentflowing through the inductor by closing the first and second switches,during a discharge phase, increase the regulated voltage and charge thecapacitor with the inductor current by closing the third and fourthswitches, and regulate a duration of the charge phase or the dischargephase such that the regulated voltage corresponds to a target value. 13.The electronic converter of claim 1, further comprising: the inductorcoupled between the first inductor terminal and the second inductorterminal; and the capacitor coupled between the first output terminaland the second output terminal.
 14. The electronic converter of claim 1,wherein the electronic converter is configured to provide the regulatedvoltage to an audio system.
 15. An integrated circuit comprising: afirst input pin or pad and a second input pin or pad, the first andsecond input pins or pads configured to receive a supply voltage acrossthe first and second input pins or pads wherein the second input pin orpad is configured to receive a ground voltage; a first output pin or padand a second output pin or pad, the first and second output pins or padsconfigured to provide a regulated voltage across the first and secondoutput pins or pads, wherein a first floating voltage at the firstoutput pin or pad is configured to vary with respect to the groundvoltage while the first and second output pins or pads provide theregulated voltage across the first and second output pins or pads, thefirst and second output pins or pads being configured to be connected toa capacitor; a first inductor pin or pad and a second inductor pin orpad configured to be coupled to an inductor; a first electronic switchcoupled between the first input pin or pad and the first inductor pin orpad; a second electronic switch coupled between the second inductor pinor pad and the second input pin or pad; a third electronic switchcoupled between the second inductor pin or pad and the first output pinor pad; a fourth electronic switch coupled between the first inductorpin or pad and the second output pin or pad; and a control circuitconfigured to: monitor the regulated voltage, during a charge phase,increase an inductor current flowing through the inductor by closing thefirst and second electronic switches, during a discharge phase, increasethe regulated voltage and charge the capacitor with the inductor currentby closing the third and fourth electronic switches, and regulate aduration of the charge phase or the discharge phase such that theregulated voltage corresponds to a target value.
 16. The integratedcircuit of claim 15, the capacitor coupled between the first output pinor pad and the second output pin or pad.
 17. A method of operating anelectronic converter, the method comprising: monitoring a regulatedvoltage between a first output terminal and a second output terminal ofthe electronic converter; during a charge phase, increasing an inductorcurrent flowing through an inductor by closing a first switch and asecond switch of the electronic converter, wherein the first switch iscoupled between a first terminal of a power supply and a first terminalof the inductor and the second switch is coupled between a secondterminal of the inductor and a second terminal of the power supply;during a discharge phase, increasing the regulated voltage and charginga capacitor operatively coupled between the first and second outputterminals with the inductor current by closing a third switch and afourth switch of the electronic converter, wherein the third switch iscoupled between the second terminal of the inductor and the first outputterminal and the fourth switch is coupled between the second terminal ofthe inductor and the second output terminal; and regulating a durationof the charge phase or the discharge phase such that the regulatedvoltage corresponds to a target value.
 18. The method of claim 17,further comprising: comparing the regulated voltage with the targetvalue at an end of the discharge phase; increasing a duration of thecharge phase when the regulated voltage is smaller than the targetvalue; and decreasing the duration of the charge phase when theregulated voltage is greater than the target value.
 19. A method ofoperating an electronic converter, the method comprising: monitoring aregulated voltage between a first output terminal and a second outputterminal of the electronic converter; during a charge phase, increasingan inductor current flowing through an inductor by closing a firstswitch and a second switch of the electronic converter, wherein thefirst switch is coupled between a first terminal of a power supply and afirst terminal of the inductor and the second switch is coupled betweena second terminal of the inductor and a second terminal of the powersupply; during a discharge phase, increasing the regulated voltage andcharging a capacitor coupled between the first and second outputterminals with the inductor current by closing a third switch and afourth switch of the electronic converter, wherein the third switch iscoupled between the second terminal of the inductor and the first outputterminal and the fourth switch is coupled between the second terminal ofthe inductor and the second output terminal; regulating a duration ofthe charge phase or the discharge phase such that the regulated voltagecorresponds to a target value; monitoring a second regulated voltagebetween a third output terminal of the electronic converter and thesecond terminal of the power supply; during a second discharge phase,increasing the second regulated voltage and charging a second capacitorwith the inductor current by closing a fifth switch and a sixth switch,wherein the second capacitor is coupled between the second outputterminal and the second terminal of the power supply, the fifth switchis coupled between the first terminal of the inductor and the secondterminal of the power supply, and the sixth switch is coupled betweenthe second terminal of the inductor and the third output terminal; andregulating a duration of the charge phase or the second discharge phasesuch that the second regulated voltage corresponds to a second targetvalue.
 20. The method of claim 19, further comprising repeatingperiodically the charge phase, the discharge phase, and the seconddischarge phase, wherein one of the discharge phase and the seconddischarge phase corresponds to a last discharge phase and the other ofthe discharge phase and the second discharge phase corresponds to anintermediate discharge phase between the charge phase and the lastdischarge phase.
 21. The method of claim 20, further comprising stoppingthe intermediate discharge phase when a respective voltage of theregulated voltage or the second regulated voltage being increased duringthe intermediate discharge phase reaches a respective target value ofthe target value or the second target value.
 22. The method of claim 17,wherein the power supply is a battery of a car.
 23. The electronicconverter of claim 1, wherein the capacitor is directly connectedbetween the first output terminal and the second output terminal. 24.The method of claim 17, further comprising: receiving a first supplyvoltage at the first terminal of the power supply; receiving a groundvoltage at the second terminal of the power supply; providing a firstfloating voltage at the first output terminal so that the first floatingvoltage varies with respect to the ground voltage while the regulatedvoltage between the first and second output terminals correspond to thetargeted value.
 25. The method of claim 24, further comprising:providing a reference voltage that is proportional to the first supplyvoltage; generating the first floating voltage based on the referencevoltage; and varying the first supply voltage with respect to the groundvoltage so that the first floating voltage varies with respect to theground voltage.